1. Technical Field
The present invention relates to a semiconductor device and a method for producing a semiconductor device.
2. Description of the Related Art
Phase-change memories are an emerging memory technology (for example, refer to Japanese Unexamined Patent Application Publication No. 2012-204404) for storing data by recording changes in resistance of data memory elements in memory cells.
The mechanism of phase-change memories involves supplying an electric current between a bit line and a source line by turning a cell transistor ON so that heat generated from a heater of a high-resistance element melts chalcogenide glass (GST: Ge2Sb2Te5) in contact with that heater and induces transition. Melting at high temperature (high current) and cooling at a high cooling rate (stopping the supply of current) generate an amorphous state (reset operation). Melting at a relatively low high temperature (low current) and cooling at a low cooling rate (gradually decreasing the current) result in crystallization (set operation). When data is being read, a high current flowing between the bit line and the source line (low resistance=crystalline state) indicates a binary 0, and a low current (high resistance=amorphous) indicates a binary 1 (for example, refer to Japanese Unexamined Patent Application Publication No. 2012-204404).
The reset current used in these memories is as high as 200 μA, for example. In order to cause such a high reset current to flow in a cell transistor, the size of the memory cell needs to be large. A selective element of a bipolar transistor or a diode can be used (for example, refer to Japanese Unexamined Patent Application Publication No. 2012-204404) in order to allow high current to flow.
Since a diode is a two-terminal element, in order to select a memory cell, selecting one source line causes electric current of all memory cells connected to that source line to flow in that one source line. Therefore, an IR drop attributable to the resistance of the source line is large.
In contrast, a bipolar transistor is a three-terminal element. However, since current flows in the base, it is difficult to connect a large number of transistors to a word line.
Decreasing the cross-sectional areas of a GST film and a heater element in the direction of the flow of the electric current decreases the reset current and the read current. Typically, a heater element is formed on a side wall of a gate of a flat transistor and a GST film is formed on top of the gate so as to decrease the cross-sectional areas of the GST film and the heater element in the direction of the flow of the electric current. According to this approach, a cell string of flat transistors is necessary (for example, refer to Japanese Unexamined Patent Application Publication No. 2012-204404).
A surrounding gate transistor (hereinafter referred to as an SGT) that includes a source, a gate, and a drain arranged in a direction perpendicular to a substrate, and a gate electrode surrounding a pillar-shaped semiconductor layer has been proposed (for example, refer to Japanese Unexamined Patent Application Publication No. 2004-356314). Since the source, gate, and drain are arranged in a direction perpendicular to the substrate, a small cell area can be achieved.